2DSC

Breaking the width-scaling limit in high-performance atomically thin 2D nanoribbon transistors

arXiv:2606.04219v1 Announce Type: cross Abstract: State-of-the-art transistors have been successfully scaled the gate lengths and channel thicknesses down to 5 nm for high-performance and energy-efficient information processing. However, reducing channel width below 40-50 nm remains a bottleneck, as dangling bonds, edge disorder, and lateral depletion suppress drive current and degrade device performance. Here, we break this width-scaling wall using ultra-scaled two-dimensional semiconductor...