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Hierarchical Recursive Precision for Accelerating Symmetric Linear Solves on MXUs
Announce Type: replace Abstract: Symmetric positive-definite system solvers based on Cholesky factorization are fundamental to many scientific applications, such as climate modeling. We present a portable, nested recursive mixed-precision solver designed for Matrix Processing Units (MXUs), including NVIDIA Tensor Cores (H200) and AMD Matrix Cores (MI300X), that assigns low-precision FP16 arithmetic to large off-diagonal blocks, while preserving high precision on diagonal blocks to ensure...
Upstart chipmakers keep challenging Nvidia. This time it's Microsoft-backed D-Matrix
In the increasingly competitive AI chip market, there's another startup in production that claims an advantage over Nvidia, the world's most valuable company. D-Matrix, located three miles away from Nvidia's Silicon Valley headquarters, says its chips can run inference workloads 10 times faster and using five times less energy than a standalone graphics processing unit from the market leader — as long as the workloads are small. The new inference chip, called Corsair, takes a novel approach...
MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs
Announce Type: new Abstract: AI model architectures are diversifying rapidly. Although dense matrix multiplication underlies today's CNNs and transformers, emerging architectures (state-space models, long convolutions via the fast Fourier transform (FFT), Kolmogorov-Arnold networks, and spiking networks) are not multiply-accumulate (MAC) dominated; they spend much of their computation on vector and non-MAC primitives that homogeneous, MAC-centric neural processing units (NPUs) serve poorly....
Heterogeneous Mapping for Analog In-Memory Computing Accelerators: A Unified Workflow
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Multi-view imaging in networked sensing systems: A covariance-based approach
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MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs
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Ahoy, DECmate II the little PDP-8 that could
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Ultrafast machine learning on FPGAs via Kolmogorov-Arnold Networks
Ultrafast machine learning on FPGAs via Kolmogorov-Arnold Networks This post is a high-level explainer for my Master’s thesis, which involves designing hardware architectures for ultrafast inference and online learning using the Kolmogorov-Arnold Network (KAN) architecture. I’ll assume familiarity with standard machine learning concepts, as well as some understanding of hardware and digital circuits; read my previous post here for the latter. Please read the two papers below for more...
The Unreasonable Redundancy of Nature's Protein Folds
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