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State-Conditional Adversarial Learning: An Off-Policy Visual Domain Transfer Method for End-to-End Imitation Learning
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Microarchitectural Co-Optimization for Sustained Throughput of RISC-V Multi-Lane Chaining Vector Processors
arXiv:2604.22314v2 Announce Type: replace Abstract: Modern RISC vector processors rely on multi-lane parallelism and chaining to achieve high sustained throughput, yet practical execution often deviates from the ideal reference due to microarchitectural inefficiencies. This work targets the open-source RVV processor Ara and analyzes its sustained-throughput loss under a fixed hardware configuration. We first establish an ideal multi-lane chaining model that decomposes ideal execution into...