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Related Articles from SNS
Absorption and Phase-Contrast Microtomography Using Direct X-ray Detection With COTS CMOS Sensors
Announce Type: replace-cross Abstract: This work presents a high-resolution X-ray microtomography system that uses commercial off-the-shelf (COTS) CMOS image sensors as direct detectors, relying on the sensor s intrinsic resolution to achieve tomographic reconstructions without optical components. The system employs a microfocus X-ray source in cone-beam geometry, enabling both absorption-contrast and propagation-based phase-contrast imaging.
ThermoPix: A High-Spatial-Resolution ElectronicPhotonic Temperature Sensor Array With Microsecond Row Readout
Announce Type: new Abstract: This paper presents ThermoPix, a CMOS-compatible electronic-photonic architecture for high-spatial-resolution temperature sensing. The proposed system converts temperature-induced wavelength shifts in a photonic interferometric sensor into timing information that can be processed by CMOS circuitry. We use a valley photonic crystal Mach-Zehnder interferometer (VPCMZI) as the sensing element, whose temperature-dependent spectral response is detected using an...
NeuDW-CIM: a 65-nm 0.8-pJ/Sop Reconfigurable Neuromorphic Compute-in-Memory Macro with Nonlinear Dendrites and K-Winners
arXiv:2606.08947v1 Announce Type: new Abstract: This work presents NeuDW-CIM, a highly efficient neuromorphic Compute-in-Memory (CIM) macro for Spiking Neural Networks (SNNs) implemented in 65 nm CMOS. The design introduces a custom twin 9T bit-cell for ternary in-puts/weights and a reconfigurable non-linear In-Memory ADC (IMA).
20 ps Non-Destructive Read and 1 ns Write Operations at <5 V in Ferroelectric HfO2/ZrO2 Non-Volatile Memories
arXiv:2606.03677v1 Announce Type: new Abstract: Achieving low-voltage, nanosecond multi-level programming and non-destructive read-out of ferroelectric non-volatile memories (NVM) is critical for analog in-memory computing architectures relying on ferroelectric capacitive devices (FeCap). We integrate HfO2/ZrO2 ferroelectric nanolayers concurrently in the BEOL of CMOS and on SiO2/Si, achieving nanosecond multilevel switching with programming voltages below 5 V. Partial ferroelectric...
Overview of the ALICE ITS3 Upgrade
Announce Type: new Abstract: The ALICE experiment will replace its three innermost tracking layers with the Inner Tracking System 3 (ITS3) during LHC Long Shutdown 3. This upgrade introduces the first fully cylindrical, wafer-scale silicon vertex detector, utilising Monolithic Active Pixel Sensors (MAPS) fabricated in a 65nm CMOS process. By thinning sensors to 50$\mu$m and bending them to radii as small as 19mm, the design achieves a self-supporting structure that eliminates traditional...
Ahoy, DECmate II the little PDP-8 that could
Now, that's a lot of word processing. But under the hood it's still at least PDP-8 adjacent, even considering its oddities and incompatibilities, and you can make it do many of the things a full-size Eight can. We'll take this basic unit, convert the floppy drives to solid state, tap the video output, and put it through its paces.
CRAM-ER: Error-Resilient Spintronic Computational Random Access Memory for Scalable In-Memory Computation
arXiv:2606.02781v1 Announce Type: new Abstract: Deep neural networks (DNNs) have achieved state-of-the-art performance across diverse domains. However, typical Von Neumann compute paradigms face severe memory bottlenecks. Emerging near-memory and compute-in-memory approaches alleviate this but incur significant peripheral overhead.
Memristor-Based Spiking Neural Network Accelerator for Bio-inspired Interception Task
arXiv:2605.31299v1 Announce Type: new Abstract: Spiking neural networks (SNNs) provide event-driven and low-power computation inspired by biological neural systems, but current implementations rely on von Neumann graphics processing units (GPUs) and central processing units (CPUs) platforms, where memory and computation bottlenecks limit energy efficiency. To address this challenge, this paper proposes an analog memristor-based spiking neural network (SNN) accelerator that integrates...
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A 65 nm Trustworthy Hypoglycemia Forecasting Engine Achieving 11.3 nJ per Inference
arXiv:2606.07455v1 Announce Type: new Abstract: Diabetes affects millions of people and requires reliable continuous glucose monitoring for early hypoglycemia warning. However, medical AI systems must be not only accurate and energy efficient, but also explainable, noise robust, and uncertainty aware. This work presents a 65 nm hypoglycemia forecasting engine based on probabilistic decision trees for trustworthy medical inference.