Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification
No mentions found
This entity hasn't been tracked yet, or Iris is still building its knowledge base.
Related Articles from SNS
VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification
Announce Type: replace Abstract: As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly.