VerilogEval

CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

arXiv:2606.05680v1 Announce Type: new Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design. Unlike typical natural language (and software coding) tasks, LLM-based RTL code generation demands strict cycle accuracy with concurrency, where minor logical errors can render a circuit unusable or insecure.