History is littered with the ruins of failed memory technologies. But former Intel CEO Pat Gelsinger believes an emerging memory tech developed by researchers at Georgia Tech using oxide semiconductors may be the exception to the rule.
"Essentially, we’ve had no major forms of innovation in memory for three decades – SRAM, DRAM, and Flash as the only memory types in broad deployment," Gelsinger told El Reg.
Nagare Labs' Z2RAM aims to change that by delivering a memory tech that's nearly as fast as SRAM at a density much closer to that of DRAM, while also being easier to manufacture than HBM or LPDDR.
"Fundamentally, they are combining the best characteristics of DRAM, SRAM, and flash into a new device that is both dense like DRAM, fast like SRAM, and scalable like flash," Gelsinger said. "While HBM has many limitations (power, density, shoreline bandwidth) the combination of its density and performance is the best available today. This is exactly the value that Z2RAM brings, giving better density, speed and power."
This explains why investor Playground Global, where Gelsinger became a partner last year, is helping to bankroll Nagare's development efforts.
SRAM-like speed, DRAM-like density
Founded by Georgia Institute of Technology professors Sumem Datta and Shimeng Yu, Nagare Labs is the culmination of years of research into next-generation memory technologies like ferroelectrics and resistive RAM.
The technology is being built on oxide semiconductors and is designed to be integrated directly onto compute logic using 3D hybrid bonding technologies. In this respect, Z2RAM will fill a similar role to AMD's 3D V-Cache SRAM stacking tech.
If you're familiar with CPUs requiring additional L3 cache, AMD uses advanced packaging to bond a 64MB SRAM tile either above or below its CPU chiplets, effectively tripling their SRAM capacity.
Z2RAM is similar in concept, but promises bit density upwards of 5x that of SRAM in its first incarnation. So if you were to look at a 64MB SRAM tile, Nagare's Z2RAM tiles would offer 320 MB of capacity in the same space, at bandwidth comparable to SRAM.
While that may not sound like a lot of capacity compared to HBM-heavy accelerators like Nvidia's Rubin with its 288 GB capacity, or AMD's MI455X with its 432 GB, Z2RAM presents a major improvement over SRAM-based accelerators like Nvidia's Groq LPUs.
Today, Nvidia's Groq 3 LPUs feature about 500 MB of SRAM per chip, necessitating thousands of accelerators in order to serve frontier LLMs at scale. Z2RAM could cut the number of chips required by 5x or more.
"With the explosion of AI demand, we’ve seen an extraordinary demand in memory as AI is a memory-limited workload. With that backdrop, there is extraordinary interest and now capital available for a breakthrough that solves the bandwidth and capacity challenges that AI is creating," Gelsinger told us.
Look Ma, no capacitors
Nagare achieves this density and bandwidth feat using memory cells based on transistors rather than capacitors.
"In terms of speed, it's going to rival SRAM, but in terms of functionality, it is more like a DRAM because of the storage mechanism," cofounder Datta told us. "DRAM is one transistor, one capacitor, one passive physical capacitor. Z2RAM is actually two transistors, but ... we are using the gate capacitance of the second transistor to store the charge."
Because that charge is stored in a transistor, reading it becomes non-destructive, which allows for better latency than you would get from DRAM. That's because when a DRAM cell is read from memory, its capacitor is drained. "After your reading is complete, you have to write back into the cell," he explained.
The fully transistor-based architecture isn't Z2RAM's only party trick because Nagare is pursuing a technology and process which will allow it to stack these cells vertically.
While that might sound a lot like HBM or LPDDR, Datta says it's actually more akin to how NAND is built up in layers, which in theory means that Z2RAM should be dramatically cheaper and easier to manufacture.
A long road ahead
With its first seed funding round behind it, Nagare now has $5 million to further the development of the tech. As semiconductor technologies go, this isn't a lot of money, but Datta is also the first to admit the startup's tech has barely left the lab.
"Where we are is literally lab prototypes," he said. The company is currently looking for an R&D fab partner to help it scale production beyond the university clean room, with the goal of sampling working Z2RAM memory tiles within the next four years and a goal of production shipments within the next decade.
Datta says the company is also open to working directly with chipmakers to integrate Z2RAM into their designs, similar to how AMD worked with TSMC on its 3D V-Cache tiles.
The company also faces challenges with regard to integration.
"There's no standard that we have right now to integrate this new memory with the accelerator," Yu said. "To unleash the benefits of this high capacity, high-speed memory, we have to use 3D bonding, and right now there's no standardization for that."
"AMD, of course, has the V-Cache, but it's a proprietary technology," he added.
In order for Z2RAM to see wide adoption without an open industry standard, Yu tells us that Nagare may have to design an interface itself, which is no small task.
There are also validation concerns. Nagare is working with oxide semiconductors, which Datta tells us benefit from better thermal and radiation performance, but are also prone to atomic vacancies.
Even "single electron effects or few electron effects can cause the threshold voltage of the transistors to move just a wee amount, and that will be enough to actually upset that cell," he explained.
Because of this, a lot of effort is going into maximizing the reliability of the Z2RAM memory cells.
"There have been so many memory startups and they didn't succeed," Datta said. "You might have the most amazing memory technology, but you can never penetrate the system because of the stringent standards."
However, Datta believes the landscape has changed. Changing dynamics and the emergence of new protocols have opened the door to being adventurous with memory again. ®